A one-transistor dynamic memory cell includes a pass-gate, a storage capacitor, and electrical connections to a bit-line, a word-line, and a capacitor plate. The trend has been to decrease the size of the memory cell, to provide higher packing density, while increasing device operating speed. Current memory cells include either deep trench capacitors or back end of line (BEOL) stacked capacitors. However, these solutions are formidable and complex to manufacture.
A need therefore exists for improved methodology enabling the manufacture of DRAM cells with effective capacitance, and the resulting devices.